module CLED (
    input   wire        clk,
    input   wire        rst_n,
    input   wire[15:0]  par,
    input   wire[15:0]  max_par,
    input   wire[4:0]   led_num,
    output  reg [3:0]   led,     
    output  reg [3:0]   gate
);

reg[3:0] sled;

always @(*) begin
    case (led_num)
        0 : begin sled = 4'b1110; gate = 4'b1110; end
        1 : begin sled = 4'b1101; gate = 4'b1110; end
        2 : begin sled = 4'b1011; gate = 4'b1110; end
        3 : begin sled = 4'b0111; gate = 4'b1110; end
        4 : begin sled = 4'b1110; gate = 4'b1101; end
        5 : begin sled = 4'b1101; gate = 4'b1101; end
        6 : begin sled = 4'b1011; gate = 4'b1101; end
        7 : begin sled = 4'b0111; gate = 4'b1101; end
        8 : begin sled = 4'b1110; gate = 4'b1011; end
        9 : begin sled = 4'b1101; gate = 4'b1011; end
       10 : begin sled = 4'b1011; gate = 4'b1011; end
       11 : begin sled = 4'b0111; gate = 4'b1011; end
       12 : begin sled = 4'b1110; gate = 4'b0111; end
       13 : begin sled = 4'b1101; gate = 4'b0111; end
       14 : begin sled = 4'b1011; gate = 4'b0111; end
       15 : begin sled = 4'b0111; gate = 4'b0111; end
       default : begin sled = 4'b1111; gate = 4'b1111; end
    endcase
end

reg[15:0] cpar;
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cpar <= 0;
        led <= 4'b1111;
    end else begin
        if (cpar == max_par) begin
            led <= sled;
            cpar <= 0;
        end else if(cpar == par) begin
            led <= 4'b1111;
            cpar <= cpar + 1;
        end else begin
            led <= led;
            cpar <= cpar + 1;
        end
    end
end

endmodule 